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generalplus technology inc. reserves the right to change this documentation without prior notice. information provided by gene ralplus technology inc. is believed to be accurate and reliable. however, generalplus technology inc. makes no warranty for any errors which may appea r in this document. contact generalplus technology inc. to obtain the latest version of device specifications before placing your order. no responsibility is assumed by generalplus technology inc. for any infringement of patent or other rights of third parties which may result from its use. in addition, ge neralplus products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of t he product may reasonably be expected to result in significant injury to the user, without the express written approval of generalplus. apr. 26, 2011 version 1.2 g g p p r r 2 2 5 5 l l 6 6 4 4 2 2 b b 64m-bit [x 1 / x 2] coms serial flash
gpr25l642b ? generalplus technology inc. proprietary & confidential 2 apr. 26, 2011 version: 1.2 table of contents page 1. features....................................................................................................................... ........................................................................... 4 1.1. g eneral ............................................................................................................................... ............................................................... 4 1.2. p erformance ............................................................................................................................... ....................................................... 4 1.3. s oftware f eatures ............................................................................................................................... ............................................ 4 1.4. h ardware f eatures ............................................................................................................................... ........................................... 4 2. general description .................................................................................................................... ...................................................... 5 3. pin configurations ................................................................................................................. ............................................................ 5 4. pin description.................................................................................................................... .................................................................. 5 5. block diagram ........................................................................................................................ .............................................................. 6 6. memory organization ................................................................................................................... ..................................................... 7 7. device operation ...................................................................................................................... ........................................................... 8 8. data protection..................................................................................................................... .............................................................. 9 9. hold features....................................................................................................................... .............................................................. 11 10. command description .................................................................................................................... .................................................. 12 10.1. w rite e nable (wren)......................................................................................................................... ............................................. 13 10.2. w rite d isable (wrdi) ......................................................................................................................... ............................................. 13 10.3. r ead s tatus r egister (rdsr)......................................................................................................................... ............................... 13 10.4. w rite s tatus r egister (wrsr)......................................................................................................................... ............................. 14 10.5. r ead d ata b ytes (read) ......................................................................................................................... ........................................ 14 10.6. r ead d ata b ytes at h igher s peed (fast_read) .................................................................................................................... ..... 14 10.7. d ual o utput m ode (dread) ........................................................................................................................ ................................... 15 10.8. s ector e rase (se) ........................................................................................................................... ................................................ 15 10.9. b lock e rase (be) ........................................................................................................................... .................................................. 15 10.10. c hip e rase (ce) ........................................................................................................................... ................................................ 15 10.11. p age p rogram (pp) ........................................................................................................................... .......................................... 15 10.12. d eep p ower - down (dp) ........................................................................................................................... .................................... 16 10.13. r elease from d eep p ower - down (rdp), r ead e lectronic s ignature (res)......................................................................... 16 10.14. r ead i dentification (rdid) ......................................................................................................................... ................................ 16 10.15. r ead e lectronic m anufacturer id & d evice id (rems).......................................................................................................... 16 10.16. e nter s ecured otp (enso)......................................................................................................................... .............................. 17 10.17. e xit s ecured otp (exso) ......................................................................................................................... ................................. 17 10.18. r ead s ecurity r egister (rdscur)....................................................................................................................... .................... 17 10.19. w rite s ecurity r egister (wrscur)....................................................................................................................... .................. 17 11. power-on state.......................................................................................................................... ......................................................... 18 11.1. i nitial d elivery s tate ............................................................................................................................... ........................................ 18 12. electrical specifications ................................................................................................................. ............................................ 19 12.1. a bsolute m aximum r atings ............................................................................................................................... .............................. 19 12.2. c apacitance ta = 25c, f = 1.0 mh z ............................................................................................................................... ................. 19 12.3. t iming a nalysis ............................................................................................................................... .................................................. 23 13. operating conditions ..................................................................................................................... ................................................. 33 13.1. a t d evice p ower -u p and p ower -d own ............................................................................................................................... ........... 33
gpr25l642b ? generalplus technology inc. proprietary & confidential 3 apr. 26, 2011 version: 1.2 14. erase and programming performance .................................................................................................................... ................ 34 14.1. d ata r etention ............................................................................................................................... ................................................. 34 14.2. l atch - up c haracteristics ............................................................................................................................... ................................ 34 15. package/pad locations ...................................................................................................................... ............................................. 35 15.1. o rdering i nformation ............................................................................................................................... ...................................... 35 15.2. p ackage i nformation ............................................................................................................................... ........................................ 35 15.2.1. title: package outline for sop 8l (209mil) ..................................................................................... ................................. 35 15.2.2. dimensions (inch dimensi ons are derived from the or iginal mm dimensions) ....................................................... ............ 35 16. disclaimer..................................................................................................................... ........................................................................ 37 17. revision history ........................................................................................................................ ......................................................... 38
gpr25l642b ? generalplus technology inc. proprietary & confidential 4 apr. 26, 2011 version: 1.2 64m-bit[x1 / x2] cmos serial flash 1. features 1.1. general ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? serial peripheral interface compatible -- mode 0 and mode 3 ? 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (dual output mode) structure ? 2048 equal sectors with 4k byte each - any sector can be erased individually ? 128 equal blocks with 64k byte each - any block can be erased individually ? program capability - byte base - page base (256 bytes) ? latch-up protected to 100ma from -1v to v cc +1v ? gpr25l642b is compatible with mx25l6406e 1.2. performance ? high performance - fast access time: 86mhz serial clock - serial clock of dual output mode: 80mhz - fast program time: 1.4ms(typ.) and 5ms(max.)/page - byte program time: 9us (typical) - fast erase time: 60ms(typ.) /sector ; 0.7s(typ.) /block ? low power consumption - low active read current: 25ma(max.) at 86mhz - low active programming current: 20ma (max.) - low active erase current: 20ma (max.) - low standby current: 50ua (max.) - deep power-down mode 5ua (typical) ? typical 100,000 erase/program cycles ? 20 years of data retention 1.3. software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp3~bp0 status bit defines the size of the area to be software protection against progr am and erase instructions - additional 512 bit secured otp for unique identifier ? auto erase and auto program algorithm - automatically erases and verifies data at selected sector - automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programmed should have page in the erased state first) ? status register feature ? electronic identification - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems commands for 1-byte manufacturer id and 1-byte device id 1.4. hardware features ? package - 8-pin sop (209mil) - rohs compliant
gpr25l642b ? generalplus technology inc. proprietary & confidential 5 apr. 26, 2011 version: 1.2 2. general description the device feature a serial per ipheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk) , a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in dual output read mode, the si and so pins become sio0 and sio1 pins for data output. the device provides sequential read operation on whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be ex ecuted. program command is executed on byte basis, or page bas is, or word basis for erase command is executes on sector, or block, or whole chip basis. to provide user with ease of in terface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security feat ures section for more details. when the device is not in operation and cs# is high, it is put in standby mode. the device reliably stores memory contents even after typical 100,000 program and erase cycles. 3. pin configurations 8-pin sop (209 mil) 4. pin description symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for dual output mode) so/sio1 serial data output (for 1 x i/o)/ serial data output (for dual output mode) sclk clock input wp# write protection hold# hold, to pause the dev ice without deselecting the device vcc + 3.3v power supply gnd ground
gpr25l642b ? generalplus technology inc. proprietary & confidential 6 apr. 26, 2011 version: 1.2 5. block diagram
gpr25l642b ? generalplus technology inc. proprietary & confidential 7 apr. 26, 2011 version: 1.2 6. memory organization table 1. memory organization block sector address range 2047 7ff000h 7fffffh ? ? ? 127 2032 7f0000h 7f0fffh 2031 7ef000h 7effffh ? ? ? 126 2016 7e0000h 7e0fffh ? ? ? ? 15 00f000h 00ffffh ? ? ? 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 0 000000h 000fffh
gpr25l642b ? generalplus technology inc. proprietary & confidential 8 apr. 26, 2011 version: 1.2 7. device operation 1. before a command is issued, status register should be checked to ensure device is r eady for the intended operation. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. the cs# falling time needs to follow tchcl spec. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. the cs# rising time needs to follow tclch spec. 4. input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown in figure 1. 5. for the following instructions: rdid, rdsr, rdscur, read, fast_read, dread, res, and rems the shift- ed-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, ce, pp, rdp, dp, enso, exso, and wrscur, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is neglected and not affect the current operation of write status register, program, erase. figure3. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cp ha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported.
gpr25l642b ? generalplus technology inc. proprietary & confidential 9 apr. 26, 2011 version: 1.2 8. data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the state machine in the standby mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. t he device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - write disable (wrdi) command completion - write status register (wrsr) command completion - page program (pp) command completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) command completion ? deep power down mode: by entering deep power down mode, the flash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res). ? advanced security features: there are some protection and security features which protect content from inadvertent write and hostile access. i. block lock protection - the software protected mode (spm): gpr25l642b: use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area definition is shown as table of "protected area sizes", the protected areas are more flexible which may protect various area by setting value of bp0-bp3 bits. please refer to table of "protected area sizes". - the hardware protected mode (hpm) uses wp# to protect the gpr25l642b: bp3-bp0 bits and srwd bit. table 2. protected area sizes status bit protect level bp3 bp2 bp1 bp0 64mb 0 0 0 0 0 (none) 0 0 0 1 1 (2block, block 126th-127th) 0 0 1 0 2 (4blocks, block 124th-127th) 0 0 1 1 3 (8blocks, block 120th-127th) 0 1 0 0 4 (16blocks, block 112th-127th) 0 1 0 1 5 (32blocks, block 96th-127th) 0 1 1 0 6 (64blocks, block 64th-127th) 0 1 1 1 7 (128blocks, all) 1 0 0 0 8 (128blocks, all) 1 0 0 1 9 (64blocks, 0th-63th) 1 0 1 0 10 (96blocks, block 0th-95th) 1 0 1 1 11 (112blocks, block 0th-111th) 1 1 0 0 12 (120blocks, block 0th-119th) 1 1 0 1 13 (124blocks, block 0th-123th) 1 1 1 0 14 (126blocks, block 0th-125th) 1 1 1 1 15 (128blocks, all) ii. additional 512 bit secured otp for unique identifier: to provide 512 bit one-time prog ram area for setting device unique serial number - which may be set by factory or system customer. please refer to table 3. 512 bit-secured otp definition. - security register bit 0 indicates whether the chip is locked
gpr25l642b ? generalplus technology inc. proprietary & confidential 10 apr. 26, 2011 version: 1.2 by factory or not. - to program the 512 bit secured otp by entering 512 bit secured otp mode (with enso command), and going through normal program procedure, and then exiting 512 bit secured otp mode by writing exso command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table of "security register definit ion" for security register bit definition and table of "512 bit secured otp definition" for address range definition. note: once lock-down whatever by fa ctory or customer, it cannot be changed any more. while in 512 bit secured otp mode, array access is not allowed. table 3. 512 bit secured otp definition address range size standard factory lock customer lock xxxx00~xxxx0f 128-bit esn (e lectrical serial number) xxxx10~xxxx3f 384-bit n/a determined by customer
gpr25l642b ? generalplus technology inc. proprietary & confidential 11 apr. 26, 2011 version: 1.2 9. hold features hold# pin signal goes low to hold any serial communications with the device. the hold feature will not stop the operation of write status register, programming, or erasing in progress. the operation of hold requires chip select(cs#) keeping low and starts on falling edge of hold# pin signal while serial clock (sclk) signal is being low (if seri al clock signal is not being low, hold operation will not start until serial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while serial clock(sclk) signal is being low(if serial clock signal is not being low, hold operation will not end until serial clock being low), see figure 2. figure 2. hold condition operation the serial data output (so) is high impedanc e, both serial data input (si) and serial clock (sclk) are don't care during the ho ld operation. if chip select (cs#) drives high during hold operation , it will reset the internal logic of the device. to re-star t communication with chip, the hold# must be at high and cs# must be at low.
gpr25l642b ? generalplus technology inc. proprietary & confidential 12 apr. 26, 2011 version: 1.2 10. command description table 4. command definition command (byte) wren (write enable) wrdi (write disable) wrsr (write status register) rdid (read identification) rdsr (read status register) read (read data) fast read (fast read data) 1st byte 06 (hex) 04 (hex) 01 (hex) 9f (hex) 05 (hex) 03 (hex) 0b (hex) 2nd byte ad1 ad1 3rd byte ad2 ad2 4th byte ad3 ad3 5th byte dummy action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to write new values to the status register outputs jedec id: 1-byte manufacturer id & 2-byte device id to read out the values of the status register n bytes read out until cs# goes high n bytes read out until cs# goes high command (byte) res (read electronic id) rems (read electronic manufacturer & device id) dread (double output mode command) se (sector erase) be (block erase) ce (chip erase) pp (page program) 1st byte ab (hex) 90 (hex) 3b (hex) 20 (hex) 52 or d8 (hex) 60 or c7 (hex) 02 (hex) 2nd byte x x ad1 ad1 ad1 ad1 3rd byte x x ad2 ad2 ad2 ad2 4th byte x add (note 1) ad3 ad3 ad3 ad3 5th byte dummy action to read out 1-byte device id output the manufacturer id & device id n bytes read out by dual output until cs# goes high to erase the selected sector to erase the selected block to erase whole chip to program the selected page command (byte) rdscur (read security register) wrscur (write security register) enso (enter secured otp) exso (exit secured otp) dp (deep power down) rdp (release from deep power down) 1st byte 2b (hex) 2f (hex) b1 (hex) c1 (hex) b9 (hex) ab (hex) 2nd byte 3rd byte 4th byte 5th byte action to read value of security register to set the lock-down bit as "1" (once lock-down, cannot be updated) to enter the 512 bit secured otp mode to exit the 512 bit-secured otp mode enters deep power down mode release from deep power down mode note 1: add=00h will output the manufacturer id firs t and add=01h will output device id first. note 2: it is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mod e.
gpr25l642b ? generalplus technology inc. proprietary & confidential 13 apr. 26, 2011 version: 1.2 10.1. write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, se, be, ce, and wrsr, which are intended to change the device content, should be set every time after the wren instruction setting the wel bit. the sequence is shown as figure 11. 10.2. write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence is shown as figure 12. the wel bit is reset by following situations: - power-up - write disable (wrdi) instruction completion - write status register (wrsr) instruction completion - page program (pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion 10.3. read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status regist er condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence is shown as figure 13. the definition of the status r egister bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program /erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored and not affect value of wel bit if it is applied to a protected memory area. bp3, bp2, bp1, bp0 bits. the block protect (bp3-bp0) bits, non-volatile bits, indicate the protected area (as defined in table 2) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3-bp0) bits requires the write status register (wrsr) instruction to be executed. those bits define the protected area of the memory to against page progr am (pp), sector erase (se), block erase (be) and chip erase (ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed). srwd bit. the status register wr ite disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#) pin for providing hardware protection mode. the hardware protection mode requires srwd se ts to 1 and wp# pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3-bp0) are read only. status register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) 0 bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 0 (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit 0 non-volatile bit non-volatile bit non-volatile bit non-vo latile bit volatile bit volatile bit note 1: see the table "protected area size".
gpr25l642b ? generalplus technology inc. proprietary & confidential 14 apr. 26, 2011 version: 1.2 10.4. write status register (wrsr) the wrsr instruction is for changi ng the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. th e wrsr instruction can change the value of block protect (bp3-bp0) bits to define the protected area of memory (as shown in table 1). the wrsr also can set or reset the status register write disable (srwd) bit in accordance with write protection (wp#) pin signal. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence is shown as figure 14. the wrsr instruction has no effect on b6, b1, b0 of the status register. the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status r egister cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 5. protection modes mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp3-bp0 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp3-bp0of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. note: 1. as defined by the values in the block protect (bp3-b p0) bits of the status register, as shown in table 2. as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter wp# is low or high, the wren inst ruction may set the wel bit and can change the values of srwd, bp 3-bp0. the protected area, which is defined by bp3-bp0 is at software protected mode (spm). - when srwd bit=1 and wp# is high, the wren instruction may set the wel bit can change the values of srwd, bp3-bp0. the protec ted area, which is defined by bp3-bp0 is at so ftware protected mode (spm) note: if srwd bit=1 but wp# is low, it is impossible to write the status register even if the wel bit has previously been set. it i s rejected to write the status register and not be executed. hardware protected mode (hpm): - when srwd bit=1, and then wp# is low (or wp# is low before sr wd bit=1), it enters the hardware protected mode (hpm). the dat a of the protected area is protected by software protected mode by bp3-bp0 and hardwa re protected mode by the wp# to against data modification. note: to exit the hardware protected mode requires wp# driving high once the hardware protected mode is entered. if the wp# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3-bp0. 10.5. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence is shown as figure 15. 10.6. read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence is shown as figure 16.
gpr25l642b ? generalplus technology inc. proprietary & confidential 15 apr. 26, 2011 version: 1.2 while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle. 10.7. dual output mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits(interleav e on 1i/2o pins) shift out on the falling edge of sclk at a maximum frequency ft. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruction. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence is shown as figure 17. while program/erase/write status register cycle is in progress, dread instruction is rejected without any impact on the program/erase/write status register current cycle. the dread only perform read operation. program/erase/read id/read status....operation do not support dread throughputs. 10.8. sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table 1) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most significant address) select the sector address. the sequence is shown as figure 18. the self-timed sector erase cycle ti me (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3-bp0 bits, the sector erase (se) instruction will not be executed on the page. 10.9. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the in struction is used for 64k-byte sector erase operation. a write enable (wren) instruction must execute to set the write enable la tch (wel) bit before sending the block erase (be). any address of the block (see table 1) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence is shown as figure 19. the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3-bp0 bits, the block erase (be) instruction will not be executed on the page. 10.10. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the chip erase (ce). any address of the sector (see table 1) is a valid address for chip erase (ce) instruction. the cs# must go high exactly at the byte boundary(the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex- ecuted. the sequence is shown as figure 20. the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp3-bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp3-bp0 all set to "0". 10.11. page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). if the eight least significant address bits (a7-a0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 l east significant address bits (a7-a0) are all 0). the cs# must keep during the whole page program cycle. the cs# must go high exactly at the byte boundary(the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. if
gpr25l642b ? generalplus technology inc. proprietary & confidential 16 apr. 26, 2011 version: 1.2 more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. if less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. the sequence is shown as figure 21. the self-timed page program cycle ti me (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3-bp0 bits, the page program (pp) instruction will not be executed. 10.12. deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consum ption (to entering the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence is shown as figure 22. once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instructi on. (those instructions allow the id being reading out). when power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip sele ct (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. 10.13. release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specified in table 9. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id definitions. this is not the same as rdid instruction. it is not recommended to use for new design. fo r new design, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. the sequence is shown in figure 23 and figure 24. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeatedly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. the rdp instruction is for releasing from deep power down mode. 10.14. read identification (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the manufacturer id and device id are listed as t able of "id definitions". the sequence is shown as figure 25. while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. 10.15. read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure 26. the device id values are listed in table of id definitions. if the one-byte address is initially set to 01h, then the device id will be read first and then followed by the manufacturer
gpr25l642b ? generalplus technology inc. proprietary & confidential 17 apr. 26, 2011 version: 1.2 id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. table 6. id definitions command type gpr25l642b manufacturer id memory type memory density rdid command c2 20 17 electronic id res command 16 manufacturer id device id rems command c2 16 10.16. enter secured otp (enso) the enso instruction is for entering the additional 512 bit secured otp mode. the additional 512 bit secured otp is independent from main array, which may use to store unique serial number for system identifier. after entering the secured otp mode, and then follow standard read or program, procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. please note that wrsr/wrscur commands are not acceptable during the access of secure otp r egion, once security otp is lock down, only read related commands are valid. 10.17. exit secured otp (exso) the exso instruction is for exiting the additional 512 bit secured otp mode. 10.18. read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence is shown as figure 27. the definition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory before ex- factory or not. when it is "0", it indicates non- factory lock; "1" indicates factory- lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for customer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 512 bit secured otp area cannot be update any more. while it is in 512 bit secured otp mode, array access is not allowed. table 7. security register definition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x x x x ldso (indicate if lock-down) secured otp indicator bit reserved reserved reserved reserved reserved reserved 0 = not lockdown 1 = lock-down (cannot program/erase otp) 0 = nonfactory lock 1 = factory lock volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit 10.19. write security register (wrscur) the wrscur instruction is for changing the values of security register bits. unlike write status register, the wren instruction is not required before sending wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 512 bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. the sequence is shown as figure 28.
gpr25l642b ? generalplus technology inc. proprietary & confidential 18 apr. 26, 2011 version: 1.2 11. power-on state the device is at below states when power-up: - standby mode (please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-do wn stage unless the vcc achieves below correct level: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the dev ice from data corruption and inadv ertent data change during power u p state. for further protection on the device, if the vcc does not reac h the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc re ached vcc minimum and a time delay of tvsl. please refer to the figure of "power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitabl e capacitor close to package pins is recommended.(generally ar ound 0.1uf) 11.1. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh).
gpr25l642b ? generalplus technology inc. proprietary & confidential 19 apr. 26, 2011 version: 1.2 12. electrical specifications 12.1. absolute maximum ratings rating value ambient operating temperature industrial grade -40c to 85c storage temperature -55c to 125c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v notes: 1. stresses greater than those listed under absolute maximum rati ngs may cause permanent damage to the device. this is stress rating only and functional operational sections of this s pecification is not implied. exposure to absolute maximum rating conditions for exten ded period may affect reliability. 2. specifications contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot v ss to -2.0v and v cc to +2.0v for periods up to 20ns, see figure 3 and 4. figure 3.maximum negative overshoot waveform figure 4. maximum positive overshoot waveform 12.2. capacitance ta = 25c, f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance - - 6 pf vin = 0v cout output capacitance - - 8 pf vout = 0v
gpr25l642b ? generalplus technology inc. proprietary & confidential 20 apr. 26, 2011 version: 1.2 figure 5. input test waveforms and measurement level figure 6. output loading
gpr25l642b ? generalplus technology inc. proprietary & confidential 21 apr. 26, 2011 version: 1.2 table 8. dc characteristics symbol parameter notes min. typ. max. units test conditions ili input load current 1 - - 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 - - 2 ua vcc = vcc max, vin = vcc or gnd isb1 vcc standby current 1 - - 50 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current - 5 20 ua vin = vcc or gnd, cs# = vcc 25 ma f=86mhz ft=80mhz (2 x i/o read) sclk=0.1vcc/0.9vcc, so=open 20 ma f=66mhz, sclk=0.1vcc/0.9vcc, so=open icc1 vcc read 1 - - 10 ma f=33mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 - - 20 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current - - 20 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 - - 20 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 - - 25 ma erase in progress, cs#=vcc vil input low voltage -0.5 - 0.3vcc v vih input high voltage 0.7vcc - vcc+0.4 v vol output low voltage - - 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 - - v ioh = -100ua notes: 1. typical values at vcc = 3.3v, t = 25c. these currents are valid for all product versions (package and speeds). 2. not 100% tested.
gpr25l642b ? generalplus technology inc. proprietary & confidential 22 apr. 26, 2011 version: 1.2 table 9. ac characteristics symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, pp, se, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr dc - 86 mhz frsclk fr clock frequency for read instructions dc - 33 mhz ftsclk ft clock frequency for dread instructions dc - 80 mhz fc=86mhz 5.5 - - ns tch(1) tclh clock high time fr=33mhz 13 - - ns fc=86mhz 5.5 - - ns tcl(1) tcll clock low time fr=33mhz 13 - - ns tclch(2) clock rise time (3) (peak to peak) 0.1 - - v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 - - v/ns tslch tcss cs# active setup time (relative to sclk) 7 - - ns tchsl cs# not active hold time (relative to sclk) 7 - - ns tdvch tdsu data in setup time 2 - - ns tchdx tdh data in hold time 5 - - ns tchsh cs# active hold time (relative to sclk) 7 - - ns tshch cs# not active setup time (r elative to sclk) 7 - - ns read 15 - - ns tshsl tcsh cs# deselect time write 40 - - ns tshqz(2) tdis output disable time - - 8 ns 2.7v~3.6v - - 8 ns tclqv tv clock low to output valid (cl=15pf) 3.0v~3.6v - - 6 ns tclqx tho output hold time 0 - - ns thlch hold# setup time (relative to sclk) 5 - - ns tchhh hold# hold time (relative to sclk) 5 - - ns thhch hold setup time (relative to sclk) 5 - - ns tchhl hold hold time (relative to sclk) 5 - - ns thhqx(2) tlz hold to output low-z - - 8 ns thlqz(2) thz hold# to output high-z - - 8 ns twhsl(4) write protect setup time 20 - - ns tshwl (4) write protect hold time 100 - - ns tdp(2) cs# high to deep power-down mode - - 10 us tres1(2) cs# high to standby mode without electronic signature read - - 8.8 us tres2(2) cs# high to standby mode with electronic signature read - - 8.8 us tw write status register cycle time - 5 40 ms tbp byte-program - 9 300 us tpp page program cycle time - 1.4 5 ms tse sector erase cycle time - 60 300 ms tbe block erase cycle time - 0.7 2 s tce chip erase cycle time - 50 80 s trpd1 cs# high to power-down 100 - - ns notes: 1. tch + tcl must be greater than or equal to 1/ fc. for fast read, tcl/tch=5.5/5.5. 2. value guaranteed by characterization, not 100% tested in production.
gpr25l642b ? generalplus technology inc. proprietary & confidential 23 apr. 26, 2011 version: 1.2 3. expressed as a slew-rate. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 5. test condition is shown as figure 5. 6. the cs# rising time needs to follow tclch spec and cs# falling time needs to follow tchcl spec. 12.3. timing analysis figure 7. serial input timing figure 8. output timing
gpr25l642b ? generalplus technology inc. proprietary & confidential 24 apr. 26, 2011 version: 1.2 figure 9. hold timing * si is "don't care" during hold operation. figure 10. wp# disable setup and hold timing during wrsr when srwd=1 figure 11. write enable (wren) sequence (command 06)
gpr25l642b ? generalplus technology inc. proprietary & confidential 25 apr. 26, 2011 version: 1.2 figure 12. write disable (wrdi) sequence (command 04) figure 13. read status register (rdsr) sequence (command 05) figure 14. write status register (wrsr) sequence (command 01)
gpr25l642b ? generalplus technology inc. proprietary & confidential 26 apr. 26, 2011 version: 1.2 figure 15. read data bytes (read) sequence (command 03) figure 16. read at higher speed (fast_read) sequence (command 0b)
gpr25l642b ? generalplus technology inc. proprietary & confidential 27 apr. 26, 2011 version: 1.2 figure 17. dual output read mode sequence (command 3b) figure 18. sector erase (se) sequence (command 20) note: se command is 20(hex). figure 19. block erase (be) sequence (command 52 or d8) note: be command is 52 or d8(hex).
gpr25l642b ? generalplus technology inc. proprietary & confidential 28 apr. 26, 2011 version: 1.2 figure 20. chip erase (ce) sequence (command 60 or c7) note: ce command is 60(hex) or c7(hex). figure 21. page program (pp) sequence (command 02) figure 22. deep power-down (dp) sequence (command b9)
gpr25l642b ? generalplus technology inc. proprietary & confidential 29 apr. 26, 2011 version: 1.2 figure 23. release from deep power-down (rdp) sequence (command ab) figure 24. release from deep power-down and read electronic signature (res) sequence (command ab) figure 25. read identification (rdid) sequence (command 9f)
gpr25l642b ? generalplus technology inc. proprietary & confidential 30 apr. 26, 2011 version: 1.2 figure 26. read electronic manufacturer & de vice id (rems) sequence (command 90) note: (1) add=00h will output the manufacturer's id fi rst and add=01h will output device id first. figure 27. read security register (rdscur) sequence (command 2b) figure 28. write security register (wrscur) sequence (command 2f)
gpr25l642b ? generalplus technology inc. proprietary & confidential 31 apr. 26, 2011 version: 1.2 figure 29. program/ erase flow with read array data
gpr25l642b ? generalplus technology inc. proprietary & confidential 32 apr. 26, 2011 version: 1.2 figure 30. power-up timing note: vcc (max.) is 3.6v and vcc (min.) is 2.7v. table 10. power-up timing symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 200 - us note: 1. the parameter is characterized only.
gpr25l642b ? generalplus technology inc. proprietary & confidential 33 apr. 26, 2011 version: 1.2 13. operating conditions 13.1. at device power-up and power-down ac timing illustrated in figure 31 and figure 32 are the supply vo ltages and the control signals at device power-up and power-d own. if the timing in the figures is ignored, t he device will not operate correctly. during power-up and power down, cs# needs to follow the voltage applied on vcc to keep the device not be selected. the cs# can be driven low when vcc reach v cc (min.) and wait a period of tvsl. figure 31. ac timing at device power-up symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v notes: 1. sampled, not 100% tested. 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, ts hch, tchcl, tclch in the figure, pl ease refer to "ac characteristics " table. figure 32. power-down sequence during power down, cs# need to follow the voltage drop on vcc to avoid mis-operation.
gpr25l642b ? generalplus technology inc. proprietary & confidential 34 apr. 26, 2011 version: 1.2 14. erase and programming performance parameter min. typ. (1) max. (2) unit write status register time - 5 40 ms sector erase time - 60 300 ms block erase time - 0.7 2 s chip erase time - 50 80 s byte program time (via page program command) - 9 300 us page program time - 1.4 5 ms erase/program cycle - 100,000 - cycles notes: 1. typical program and erase time assumes the followi ng conditions: 25c, 3.3v, and checker board pattern. 2. under worst conditions of 85c and 2.7v. 3. system-level overhead is the time required to execut e the first-bus-cycle sequence for the programming command. 4. erase/program cycles comply je dec: jesd-47 & j esd22-a117 standard. 14.1. data retention parameter condition min. max. unit data retention 55 ? c 20 - years 14.2. latch-up characteristics min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test c onditions: vcc = 3.0v, one pin at a time.
gpr25l642b ? generalplus technology inc. proprietary & confidential 35 apr. 26, 2011 version: 1.2 15. package/pad locations 15.1. ordering information product number package type GPR25L642B-HS13X package form - sop 8l 209mil rohs (green package) note: x = 1 - 9, serial number. 15.2. package information 15.2.1. title: package outline for sop 8l (209mil) 15.2.2. dimensions (inch dimensions are derived from the original mm dimensions) symbols a a1 a2 b c d e e1 e l l1 s min. - 0.05 1.70 0.36 0.19 5.13 7.70 5.18 - 0.50 1.21 0.62 0 nom. - 0.15 1.80 0.41 0.20 5.23 7.90 5.28 1.27 0.65 1.31 0.74 5 mm max 2.16 0.20 1.91 0.51 0.25 5.33 8.10 5.38 - 0.80 1.41 0.88 8 min. - 0.002 0.067 0.014 0.007 0.202 0.303 0.204 - 0.020 0.048 0.024 0 nom. - 0.006 0.071 0.016 0.008 0.206 0.311 0.208 0.050 0.026 0.052 0.029 5 inch max 0.085 0.008 0.075 0.020 0.010 0.210 0.319 0.212 - 0.031 0.056 0.035 8
gpr25l642b ? generalplus technology inc. proprietary & confidential 36 apr. 26, 2011 version: 1.2 reference dwg. no. revision jedec eiaj issue date 6110-1406 2
gpr25l642b ? generalplus technology inc. proprietary & confidential 37 apr. 26, 2011 version: 1.2 16. disclaimer the information appearing in this public ation is believed to be accurate. integrated circuits sold by generalplus technology are covered by the warranty and pa tent indemnification pr ovisions stipulated in the terms of sale only. generalplus makes no warranty, express, statutor y implied or by description regarding the information in this pu blication or regarding the freedom of the described chip(s) from patent infringement. furthermore, generalplus makes no warranty of merchantability or fitness for any purpose. generalp lus reserves the right to halt production or alter the specifications and prices at any time wit hout notice. accordingly, the reader is c autioned to verify that the data sheets and other information in this publication are current before placing orders. pr oducts described herein are intended for use in normal commercial app lications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equip ment, are specifically not recommended without additional processing by generalplus for such app lications. please note that application circuits illustrated in this document are for reference purposes only.
gpr25l642b ? generalplus technology inc. proprietary & confidential 38 apr. 26, 2011 version: 1.2 17. revision history date revision description page apr. 26, 2011 1.2 1. modified standby current from 100ua to 50ua. 2. modified description for rohs compliance. 3. added cs# rising and falling time description. 4. modified tclqv (15pf loading). 5. modified tw from 40ms(typ.)/100ms(max.) to 5ms(typ.)/40ms(max.). 6. added rdscur and wrscur diagram form. 4 4 8,23 22 22,34 30 dec. 14, 2010 1.1 add writer compatible information in section 1.1 4 sep. 30, 2010 1.0 original 38

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